FIG. 1 shows a prior art wireless communications receiver 100. An analog part of the receiver 102 receives wireless signals from an antenna 104, which pass through transmit/receive switches and filters 106, and to variable gain low noise amplifier 108, which typically accepts a coarse gain control input 116 for reducing the LNA gain for high signal levels and increasing the LNA gain for low signal levels, thereby keeping the mixer 110 operating linearly in a noise performance optimized operating point. Baseband mixers 110 down-convert the modulated signal to a quadrature baseband signal which is baseband filtered 111 and followed by a variable gain amplifier 112 which optimizes the signal level to the sampling range of the signal leaving the analog signal processing subsection 102 via IO buffers 114 to the A/D interface 122 where the in-phase (I) and quadrature (Q) signals are sampled by analog to digital converter 124, also known as the IQ ADC. The selection of an optimum VGA 112 gain results in the IQ ADC 124 sampling the signal to fill the linear range of the A/D converter 124, after which the signals are passed to the baseband processor 130. A received signal strength indicator (RSSI) signal 120 is typically generated by one or more of the analog processing stages, which is shown as RSSI generation function 113. The RSSI signal 120 provides a coarse indication of incoming signal strength, and is typically digitized by RSSI ADC 126 and processed by AGC processor 132 to generate the LNA gain 116 and VGA gain 118. In this manner, the prior art AGC processor samples an RSSI signal and generates gain control signals to optimize the sample range of the ADC and baseband processor 130.
The boundaries of communications receiver 100 are separated into processing sections based on the type of technology in use for that particular section. Analog processing 102 typically uses small signal amplifying elements such as linear amplifiers 108 and 112, buffers 114, and non-linear elements such as mixer 110. Typically these analog components have high current consumption for optimized high speed performance, and the power consumed by analog section 102 is a significant part of the system power. A/D Interface 122 includes high speed IQ ADC 124 which samples the down-converted and filtered baseband signal for processing and low speed ADC 126 for sampling the RSSI signal 120. The IQ ADC 124 typically operates at a much higher sampling rate (80 Mhz typically) and quantization level (10 bit) than the low speed (10 Mhz or less at 8 bit) RSSI ADC 126. The remaining components are digital signal processing elements 128 which have power consumption that is governed by the clock rate of the synchronous clock used to drive the various stages.
For battery powered wireless receivers, it is desired to reduce the power consumption, thereby proportionally increasing the life of the battery powering the receiver. The opportunities for reduced power consumption for each section of the prior art receiver 100 are somewhat limited. The analog processing 102 consumes a fixed amount of power regardless of whether a packet is being received or not, and in operating conditions where the time spent receiving packets is low compared to the time spent listening for packets to receive, a large power savings may be realized by using the IQ ADC and RSSI ADC only during the intervals when they are required. The ADC interface 122 has a power consumption which includes a fixed part and a part that is proportional to the sample rate and bit width of the ADC, and is dominated by high speed converter 124. The digital processing 128 including baseband processing 130 and AGC processor 132 are dominated by displacement currents associated with switching large numbers of signal conductors from one voltage level to another, resulting in a power consumption which is largely proportional to clock speed.